With a rapid development of Very Large Scale Integrated circuits (VLSI) technology, the silicon integrated circuit process has entered a product manufacturing stage generally based on a feature size of deep submicron and even to ultra-deep submicron. The progress of fabrication process greatly increases quality and performance of VLSI while dramatically reduces the process cost of an individual chip, thus promotes the product popularization of integrated circuit and brings a new electronic information revolution. However, the operation voltage is not able to be scaled down in a proportion while the size of the device is scaled down. Therefore, various reliability problems are gradually becoming more serious, mainly including the hot carrier effect (HCI), the negative bias thermal instability (NBTI) and an time dependent dielectric breakdown (TDDB), etc.
SOI MOSFET device is a structure in which a monocrystalline silicon film is formed over an insulating substrate or a monocrystalline silicon film is formed over a supporting silicon substrate with an insulating layer interposed therebetween for separation. Compared with a conventional bulk silicon MOS device, the SOI MOSFET has advantages such as a good characteristic of electrical isolation, a small parasitic capacitance, easy to form a shallow junction, capable of avoiding latch-up effect and a good capability of radiation resistance and so on. However, due to the quite lower thermal conductivity of buried oxide layer in the SOI MOSFET device, the lattice temperature of a channel region in the device rises, resulting in a decrease of the on-state drain current of the device.
An essential idea of the accelerated lifetime testing is to extrapolate the feature of the lifetime in a normal stress level by using the feature of the lifetime in a high stress level. A key of achieving the essential idea is to establish a relationship between the feature of the lifetime and the stress level, i.e. an acceleration model. In the conventional stress acceleration process, the applied stress condition is a direct current (DC) voltage, and a corresponding time to failure (TTF) is used to predict the lifetime for the device applied into a digital circuit and an analog circuit. However, an error may occurr when predicting a logic circuit or an AC analog circuit operated in real world by the method. The reason is that, the generation of the self-heating effect is associated with the frequency of the operating circuit. More specifically, if the operating frequency is higher, the thermal response of the device is conducted so soon that a signal has not been built yet. Meanwhile, if the operating frequency is lower, the self-heating effect is getting more serious. Thus, in predicting the lifetime of the digital circuit in the high stress level, the influence on the lifetime from the self-heating effect should be eliminated, so that an accurate value of the reliable lifetime of the SOI MOSFET can be obtained.